The present invention relates to a method of manufacturing a semiconductor device and, more particularly, to a technology related to a process of forming transistors for a high-integrated semiconductor memory device using a Silicon-On-Insulator (SOI) substrate.
In a system including a plurality of electronic components, a semiconductor memory device is used to store data. When a data processing device (e.g., a Central Processing Unit (CPU)) requests data, a semiconductor memory device outputs stored data corresponding to an address received from a data request apparatus.
With an increase in the data storage capacity of a semiconductor memory device, the size of a unit cell has gradually decreased and the size of an element for a read or write operation has also decreased. Accordingly, it is important to minimize the area occupied by elements (e.g., wirings or transistors), by integrating the elements. Further, in order to further increase the degree of integration, it is necessary to reduce the size of each of unit cells within the semiconductor memory device.
For example, in Dynamic Random Access Memory (DRAM) (i.e., a type of volatile memory device capable of storing data as long as power is applied) from among semiconductor memory devices, a unit cell within the semiconductor memory device includes one transistor and one capacitor. The area (i.e., footprint) where the capacitor is formed has decreased with a decrease in the design rule. In order to overcome this problem and increase the electrostatic capacitance of the capacitor, an effort is being made to develop a semiconductor device constituting an insulating layer within the capacitor, but have encountered many difficulties. The decrease of the design rule makes it difficult to perform normal read and write operations because the value of junction resistance at a storage node SN within the unit cell and the turn-on resistance value of the transistor rise, resulting in a poor refresh property.
An improved unit cell within a semiconductor memory device has been proposed, which includes a transistor having a floating body. In other words, a capacitor used to store data is not included in the unit cell of the semiconductor memory device, but floating in the body of the transistor within the unit cell. The floating body transistors are implemented on a general semiconductor substrate formed of a single silicon layer, but are implemented on an SOI substrate in which an insulating layer is interposed between the silicon layers.
The floating body transistors formed in the silicon layers over the insulating layer are separated from each other by an isolation layer. If the SOI substrate is used, junction capacitance occurring between the silicon layer and the floating body transistor is greatly decreased as compared with a general semiconductor substrate. Accordingly, RC delay of the transistor occurring because of resistance and capacitance can be reduced. Further, subsequent processes for manufacturing a semiconductor memory device are identical to those of the known art except that the semiconductor substrate is replaced with the SOI substrate.